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VS1033a preliminary VS1033 a VS1033 - mp3/aac/wma/midi audio codec features 2 decodes mpeg 1 & 2 audio layer iii (cbr +vbr +abr); layers i & ii optional; mpeg4 / 2 aac-lc-2.0.0.0 (+pns); wma 4.0/4.1/7/8/9 all pro?les (5-384 kbps); wav (pcm + ima adpcm); general midi / sp-midi format 0 ?les 2 encodes ima adpcm from microphone or line input 2 streaming support for mp3 and wav 2 bass and treble controls 2 operates with a single clock 12..13 mhz. 2 can also be used with 24..26 mhz clocks. 2 internal pll clock multiplier 2 low-power operation 2 high-quality on-chip stereo dac with no phase error between channels 2 stereo earphone driver capable of driving a 30 load 2 i2s interface for external dac 2 separate operating voltages for analog, dig- ital and i/o 2 5.5 kib on-chip ram for user code / data 2 serial control and data interfaces 2 can be used as a slave co-processor 2 spi ?ash boot for special applications 2 uart for debugging purposes 2 new functions may be added with software and 8 gpio pins 2 lead-free rohs-compliant package (green) description VS1033 is a single-chip mp3/aac/wma/midi audio decoder and adpcm encoder. it contains a high-performance, proprietary low-power dsp processor core vs dsp 4 , working data memory, 5 kib instruction ram and 0.5 kib data ram for user applications, serial control and input data interfaces, upto 8 general purpose i/o pins, an uart, as well as a high-quality variable-sample- rate mono adc and stereo dac, followed by an earphone ampli?er and a ground buffer. VS1033 receives its input bitstream through a se- rial input bus, which it listens to as a system slave. the input stream is decoded and passed through a digital volume control to an 18-bit oversampling, multi-bit, sigma-delta dac. the decoding is con- trolled via a serial control bus. in addition to the basic decoding, it is possible to add application speci?c features, like dsp effects, to the user ram memory. version 0.6, 2005-01-05 1 vlsi solution y instruction ram instruction rom stereo dac monoadc lr uart serialdata/ control interface stereo ear?phone driver dreqso si sclk xcs rx tx audiooutput x romx ram y rom y ram gpio gpio vsdsp 4 xdcs mic amp clockmultiplier mux lineaudio micaudio 8 i2s VS1033
VS1033a preliminary VS1033 a contents contents 1 licenses 9 2 disclaimer 9 3 de?nitions 9 4 characteristics & speci?cations 10 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 switching characteristics - boot initialization . . . . . . . . . . . . . . . . . . . . . . . 12 5 packages and pin descriptions 13 5.1 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 lqfp-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.2 bga-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 lqfp-48 and bga-49 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 connection diagram, lqfp-48 16 7 spi buses 17 7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2 spi bus pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2.1 vs1002 native modes (new mode) . . . . . . . . . . . . . . . . . . . . . . . . 17 version 0.6, 2005-01-05 2 vlsi solution y
VS1033a preliminary VS1033 a contents 7.2.2 vs1001 compatibility mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3 data request pin dreq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4 serial protocol for serial data interface (sdi) . . . . . . . . . . . . . . . . . . . . . . . 18 7.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4.2 sdi in vs1002 native modes (new mode) . . . . . . . . . . . . . . . . . . . . 18 7.4.3 sdi in vs1001 compatibility mode . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4.4 passive sdi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5 serial protocol for serial command interface (sci) . . . . . . . . . . . . . . . . . . . . 19 7.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5.2 sci read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5.3 sci write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.7 spi examples with sm sdinew and sm sdishared set . . . . . . . . . . . . . . . 22 7.7.1 two sci writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.7.2 two sdi bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.7.3 sci operation in middle of two sdi bytes . . . . . . . . . . . . . . . . . . . . 23 8 functional description 24 8.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 supported audio codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2.1 supported mp3 (mpeg layer iii) formats . . . . . . . . . . . . . . . . . . . . 24 8.2.2 supported mp1 (mpeg layer i) formats . . . . . . . . . . . . . . . . . . . . . 25 8.2.3 supported mp2 (mpeg layer ii) formats . . . . . . . . . . . . . . . . . . . . . 25 8.2.4 supported aac (iso/iec 13818-7) formats . . . . . . . . . . . . . . . . . . . 26 8.2.5 supported wma formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 version 0.6, 2005-01-05 3 vlsi solution y
VS1033a preliminary VS1033 a contents 8.2.6 supported riff wav formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2.7 supported midi formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 data flow of VS1033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.4 serial data interface (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6.1 sci mode (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.6.2 sci status (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6.3 sci bass (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6.4 sci clockf (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.6.5 sci decode time (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6.6 sci audata (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6.7 sci wram (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6.8 sci wramaddr (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6.9 sci hdat0 and sci hdat1 (r) . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.6.10 sci aiaddr (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.6.11 sci vol (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.6.12 sci aictrl[x] (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 operation 40 9.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4 adpcm recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.4.1 activating adpcm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 version 0.6, 2005-01-05 4 vlsi solution y
VS1033a preliminary VS1033 a contents 9.4.2 reading ima adpcm data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.4.3 adding a riff header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.4.4 playing adpcm data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.4.5 sample rate considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.4.6 example code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.5 spi boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.6 play/decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.7 feeding pcm data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8 extra parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.8.1 common parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.8.2 wma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.8.3 aac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.8.4 midi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.9 fast forward / rewind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.9.1 mp3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.9.2 aac - adts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.9.3 aac - adif, mp4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.9.4 wma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.9.5 midi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.10 sdi tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.10.1 sine test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.10.2 pin test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.10.3 memory test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.10.4 sci test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 version 0.6, 2005-01-05 5 vlsi solution y
VS1033a preliminary VS1033 a contents 10 VS1033 registers 53 10.1 who needs to read this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.2 the processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3 VS1033 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.4 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.5 serial data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.6 dac registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.7 gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.8 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.9 a/d modulator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.10watchdog v1.0 2002-08-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.10.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.11uart v1.1 2004-10-09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.11.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.11.2 status uartx status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.11.3 data uartx data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.11.4 data high uartx datah . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.11.5 divider uartx div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.11.6 interrupts and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.12timers v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.12.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.12.2 con?guration timer config . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.12.3 con?guration timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.12.4 timer x startvalue timer tx[l/h] . . . . . . . . . . . . . . . . . . . . . . . 63 version 0.6, 2005-01-05 6 vlsi solution y
VS1033a preliminary VS1033 a contents 10.12.5 timer x counter timer txcnt[l/h] . . . . . . . . . . . . . . . . . . . . . . 63 10.12.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.13i2s dac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.13.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.13.2 con?guration i2s config . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.14system vector tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.14.1 audioint, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.14.2 sciint, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.14.3 dataint, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.14.4 moduint, 0x23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.14.5 txint, 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.14.6 rxint, 0x25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.14.7 timer0int, 0x26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.14.8 timer1int, 0x27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.14.9 usercodec, 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.15system vector functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.15.1 writeiram(), 0x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.15.2 readiram(), 0x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.15.3 databytes(), 0x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.15.4 getdatabyte(), 0x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.15.5 getdatawords(), 0xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.15.6 reboot(), 0xc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11 document version changes 69 11.1 version 0.6 for VS1033a, 2005-01-05 . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 version 0.6, 2005-01-05 7 vlsi solution y
VS1033a preliminary VS1033 a list of figures 11.2 version 0.5, 2005-10-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12 contact information 70 list of figures 1 pin con?guration, lqfp-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 pin con?guration, bga-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 typical connection diagram using lqfp-48. . . . . . . . . . . . . . . . . . . . . . . . 16 4 bsync signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 bsync signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 sci word read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 sci word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 spi timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 two sci operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 two sdi bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 two sdi bytes separated by an sci operation. . . . . . . . . . . . . . . . . . . . . . . 23 12 data flow of VS1033. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 13 adpcm frequency responses with 8 khz sample rate. . . . . . . . . . . . . . . . . . . 33 14 users memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15 rs232 serial interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16 i2s interface, 192 khz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 version 0.6, 2005-01-05 8 vlsi solution y
VS1033a preliminary VS1033 a 1. licenses 1 licenses mpeg layer-3 audio decoding technology licensed from fraunhofer iis and thomson. note: if you enable layer i and layer ii decoding, you are liable for any patent issues that may arise from using these formats. joint licensing of mpeg 1.0 / 2.0 layer iii does not cover all patents pertaining to layers i and ii. VS1033 contains wma decoding technology from microsoft. this product is protected by certain intellectual property rights of microsoft and cannot be used or further distributed without a license from microsoft. VS1033 contains aac technology (iso/iec 13818-7) which cannot be used without a proper license from via licensing corporation or individual patent holders. to the best of our knowledge, if the end product does not play a speci?c format that otherwise would require a customer license: mpeg 1.0/2.0 layers i and ii, wma, or aac, the respective license should not be required. decoding of mpeg layers i and ii are disabled by default, and wma and aac format exclusion can be easily performed based on the contents of the sci hdat1 register. 2 disclaimer this is a preliminary datasheet. all properties and ?gures are subject to change. 3 de?nitions b byte, 8 bits. b bit. ki kibi = 2 10 = 1024 (iec 60027-2). mi mebi = 2 20 = 1048576 (iec 60027-2). vs dsp vlsi solutions dsp core. w word. in vs dsp, instruction words are 32-bit and data words are 16-bit wide. version 0.6, 2005-01-05 9 vlsi solution y
VS1033a preliminary VS1033 a 4. characteristics & specifications 4 characteristics & speci?cations 4.1 absolute maximum ratings parameter symbol min max unit analog positive supply avdd -0.3 3.6 v digital positive supply cvdd -0.3 2.7 v i/o positive supply iovdd -0.3 3.6 v current at any digital output 50 ma voltage at any digital input -0.3 iovdd+0.3 1 v operating temperature -40 +85 c storage temperature -65 +150 c 1 must not exceed 3.6 v 4.2 recommended operating conditions parameter symbol min typ max unit ambient operating temperature -40 +85 c analog and digital ground 1 agnd dgnd 0.0 v positive analog avdd 2.5 2.8 3.6 v positive digital cvdd 2.4 2.5 2.7 v i/o voltage iovdd cvdd-0.6v 2.8 3.6 v input clock frequency 2 xtali 12 12.288 13 mhz internal clock frequency clki 12 36.864 55.3 mhz internal clock multiplier 3 1 : 0 3 : 0 4 : 5 master clock duty cycle 40 50 60 % 1 must be connected together as close the device as possible for latch-up immunity. 2 the maximum sample rate that can be played with correct speed is xtali/256. thus, xtali must be at least 12.288 mhz to be able to play 48 khz at correct speed. 3 reset value is 1 : 0 . recommended sc mult= 3 : 0 , sc add= 1 : 0 (sci clockf=0x9000). version 0.6, 2005-01-05 10 vlsi solution y
VS1033a preliminary VS1033 a 4. characteristics & specifications 4.3 analog characteristics unless otherwise noted: avdd =2.5..2.85v, cvdd =2.4..2.7v, iovdd=cvdd -0.6v..3.6v, ta=-40..+85 c, xtali=12..13mhz, internal clock multiplier 3 : 5 . dac tested with 1307.894 hz full-scale output sinewave, measurement bandwidth 20..20000 hz, analog output load: left to gbuf 30 , right to gbuf 30 . microphone test amplitude 50 mvpp, f s =1 khz, line input test amplitude 1.1 v, f s =1 khz. parameter symbol min typ max unit dac resolution 18 bits total harmonic distortion thd 0.1 0.3 % dynamic range (dac unmuted, a-weighted) idr 90 db s/n ratio (full scale signal) snr 70 db interchannel isolation (cross talk) 50 75 db interchannel isolation (cross talk), with gbuf 40 db interchannel gain mismatch -0.5 0.5 db frequency response -0.1 0.1 db full scale output voltage (peak-to-peak) 1.3 1.5 1 1.7 vpp deviation from linear phase 5 analog output load resistance aolr 16 30 2 analog output load capacitance 100 pf microphone input ampli?er gain micg 26 db microphone input amplitude 50 140 3 mvpp ac microphone total harmonic distortion mthd 0.02 0.10 % microphone s/n ratio msnr 50 62 db line input amplitude 2200 2800 3 mvpp ac line input total harmonic distortion lthd 0.06 0.10 % line input s/n ratio lsnr 60 68 db line and microphone input impedances 100 k 1 3.0 volts can be achieved with +-to-+ wiring for mono difference sound. 2 aolr may be much lower, but below typical distortion performance may be compromised. 3 above typical amplitude the harmonic distortion increases. 4.4 power consumption tested with an mpeg 1.0 layer-3 128 kbps sample and generated sine. output at full volume. internal clock multiplier 3 : 0 . parameter min typ max unit power supply consumption avdd, reset 0.6 5.0 1 a power supply consumption cvdd = 2.5v, reset 3.7 50.0 1 a power supply consumption avdd, sine test, 30 + gbuf 36.9 ma power supply consumption cvdd = 2.5v, sine test 8.2 ma power supply consumption avdd, no load 7.0 ma power supply consumption avdd, output load 30 10.9 ma power supply consumption avdd, 30 + gbuf 16.1 ma power supply consumption cvdd = 2.5v 14 ma version 0.6, 2005-01-05 11 vlsi solution y
VS1033a preliminary VS1033 a 4. characteristics & specifications 4.5 digital characteristics parameter symbol min typ max unit high-level input voltage 0 : 7 iovdd iovdd+0.3 1 v low-level input voltage -0.2 0 : 3 iovdd v high-level output voltage at i o = -2.0 ma 0 : 7 iovdd v low-level output voltage at i o = 2.0 ma 0 : 3 iovdd v input leakage current -1.0 1.0 1 a spi input clock frequency 2 clki 6 mhz rise time of all output pins, load = 50 pf 50 ns 1 must not exceed 3.6v 2 value for sci reads. sci and sdi writes allow clki 4 . 4.6 switching characteristics - boot initialization parameter symbol min max unit xreset active time 2 xtali xreset inactive to software ready 16600 50000 1 xtali power on reset, rise time to cvdd 10 v/s 1 dreq rises when initialization is complete. you should not send any data or commands before that. version 0.6, 2005-01-05 12 vlsi solution y
VS1033a preliminary VS1033 a 5. packages and pin descriptions 5 packages and pin descriptions 5.1 packages both lpqfp-48 and bga-49 are lead (pb) free and also rohs compliant packages. rohs is a short name of directive 2002/95/ec on the restriction of the use of certain hazardous substances in electrical and electronic equipment . 5.1.1 lqfp-48 figure 1: pin con?guration, lqfp-48. lqfp-48 package dimensions are at http://www.vlsi.?/ . 5.1.2 bga-49 figure 2: pin con?guration, bga-49. bga-49 package dimensions are at http://www.vlsi.?/ . version 0.6, 2005-01-05 13 1 48 a bc d e f g 1 2 3 4 5 6 7 top view 0.80 typ 4.807.00 1.10 ref 0.80 typ 1.10 ref 4.807.00 a1 ball pad corner vlsi solution y
VS1033a preliminary VS1033 a 5. packages and pin descriptions 5.2 lqfp-48 and bga-49 pin descriptions pin name lqfp pin bga ball pin type function micp 1 c3 ai positive differential microphone input, self-biasing micn 2 c2 ai negative differential microphone input, self-biasing xreset 3 b1 di active low asynchronous reset, schmitt-triggered input dgnd0 4 d2 dgnd core & i/o ground cvdd0 5 c1 cpwr core power supply iovdd0 6 d3 iopwr i/o power supply cvdd1 7 d1 cpwr core power supply dreq 8 e2 do data request, input bus gpio2 / dclk 1 9 e1 dio general purpose io 2 / serial input data bus clock gpio3 / sdata 1 10 f2 dio general purpose io 3 / serial data input gpio6 11 f1 dio general purpose io 6 gpio7 12 g1 dio general purpose io 7 xdcs / bsync 1 13 e3 di data chip select / byte sync iovdd1 14 f3 iopwr i/o power supply vco 15 g2 do for testing only (clock vco output) dgnd1 16 f4 dgnd core & i/o ground xtalo 17 g3 ao crystal output xtali 18 e4 ai crystal input iovdd2 19 g4 iopwr i/o power supply iovdd3 f5 iopwr i/o power supply dgnd2 20 dgnd core & i/o ground dgnd3 21 g5 dgnd core & i/o ground dgnd4 22 f6 dgnd core & i/o ground xcs 23 g6 di chip select input (active low) cvdd2 24 g7 cpwr core power supply gpio5 / i2s mclk 3 25 e5 dio general purpose io 5 / i2s mclk rx 26 e6 di uart receive, connect to iovdd if not used tx 27 f7 do uart transmit sclk 28 d6 di clock for serial bus si 29 e7 di serial input so 30 d5 do3 serial output cvdd3 31 d7 cpwr core power supply test 32 c6 di reserved for test, connect to iovdd gpio0 / i2s sclk 3 33 c7 dio general purpose io 0 (spiboot) / i2s sclk use 100 k pull-down resistor 2 gpio1 / i2s sdata 3 34 b6 dio general purpose io 1 / i2s sdata gnd 35 b7 dgnd i/o ground gpio4 / i2s lrout 3 36 a7 dio general purpose io 4 / i2s lrout agnd0 37 c5 apwr analog ground, low-noise reference avdd0 38 b5 apwr analog power supply right 39 a6 ao right channel output agnd1 40 b4 apwr analog ground agnd2 41 a5 apwr analog ground gbuf 42 c4 ao ground buffer avdd1 43 a4 apwr analog power supply rcap 44 b3 aio filtering capacitance for reference avdd2 45 a3 apwr analog power supply left 46 b2 ao left channel output agnd3 47 a2 apwr analog ground linein 48 a1 ai line input version 0.6, 2005-01-05 14 vlsi solution y
VS1033a preliminary VS1033 a 5. packages and pin descriptions 1 first pin function is active in new mode, latter in compatibility mode. 2 unless pull-down resistor is used, spi boot is tried. see chapter 9.5 for details. 3 if i2s cf ena is 0 the pins are used for gpio. see chapter 10.13 for details. pin types: type description di digital input, cmos input pad do digital output, cmos input pad dio digital input/output do3 digital output, cmos tri-stated output pad ai analog input type description ao analog output aio analog input/output apwr analog power supply pin dgnd core or i/o ground pin cpwr core power supply pin iopwr i/o power supply pin in bga-49, d4 is a no-connect ball. version 0.6, 2005-01-05 15 vlsi solution y
VS1033a preliminary VS1033 a 6. connection diagram, lqfp-48 6 connection diagram, lqfp-48 figure 3: typical connection diagram using lqfp-48. the ground buffer gbuf can be used for common voltage (1.24 v) for earphones. this will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1033 may be connected directly to the earphone connector. unused gpio pins should have a pull-down resistor. if gbuf is not used, left and right must be provided with 100 1 f capacitors. if uart is not used, rx should be connected to iovdd and tx be unconnected. do not connect any external load to xtalo. note: this connection assumes sm sdinew is active (see chapter 8.6.1). if also sm sdishare is used, xdcs should be tied low or high (see chapter 7.2.1). version 0.6, 2005-01-05 16 vlsi solution y
VS1033a preliminary VS1033 a 7. spi buses 7 spi buses 7.1 general the spi bus - that was originally used in some motorola devices - has been used for both VS1033s serial data interface sdi (chapters 7.4 and 8.4) and serial control interface sci (chapters 7.5 and 8.5). 7.2 spi bus pin descriptions 7.2.1 vs1002 native modes (new mode) these modes are active on VS1033 when sm sdinew is set to 1 (default at startup). dclk, sdata and bsync are replaced with gpio2, gpio3 and xdcs, respectively. sdi pin sci pin description xdcs xcs active low chip select input. a high level forces the serial interface into standby mode, ending the current operation. a high level also forces serial output (so) to high impedance state. if sm sdishare is 1, pin xdcs is not used, but the signal is generated internally by inverting xcs. sck serial clock input. the serial clock is also used internally as the master clock for the register interface. sck can be gated or continuous. in either case, the ?rst rising clock edge after xcs has gone low marks the ?rst bit to be written. si serial input. if a chip select is active, si is sampled on the rising clk edge. - so serial output. in reads, data is shifted out on the falling sck edge. in writes so is at a high impedance state. 7.2.2 vs1001 compatibility mode this mode is active when sm sdinew is set to 0. in this mode, dclk, sdata and bsync are active. sdi pin sci pin description - xcs active low chip select input. a high level forces the serial interface into standby mode, ending the current operation. a high level also forces serial output (so) to high impedance state. bsync - sdi data is synchronized with a rising edge of bsync. dclk sck serial clock input. the serial clock is also used internally as the master clock for the register interface. sck can be gated or continuous. in either case, the ?rst rising clock edge after xcs has gone low marks the ?rst bit to be written. sdata si serial input. si is sampled on the rising sck edge, if xcs is low. - so serial output. in reads, data is shifted out on the falling sck edge. in writes so is at a high impedance state. version 0.6, 2005-01-05 17 vlsi solution y
VS1033a preliminary VS1033 a 7. spi buses 7.3 data request pin dreq the dreq pin/signal is used to signal if VS1033s fifo is capable of receiving data. if dreq is high, VS1033 can take at least 32 bytes of sdi data or one sci command. when these criteria are not met, dreq is turned low, and the sender should stop transferring new data. because of the 32-byte safety area, the sender may send upto 32 bytes of sdi data at a time without checking the status of dreq, making controlling VS1033 easier for low-speed microcontrollers. note: dreq may turn low or high at any time, even during a byte transmission. thus, dreq should only be used to decide whether to send more bytes. it should not abort a transmission that has already started. note: in vs10xx products upto vs1002, dreq was only used for sdi. in vs1003 and VS1033 dreq is also used to tell the status of sci. 7.4 serial protocol for serial data interface (sdi) 7.4.1 general the serial data interface operates in slave mode so dclk signal must be generated by an external circuit. data (sdata signal) can be clocked in at either the rising or falling edge of dclk (chapter 8.6). VS1033 assumes its data input to be byte-sychronized. sdi bytes may be transmitted either msb or lsb ?rst, depending of contents of sci mode (chapter 8.6.1). the ?rmware is able to accept the maximum bitrate the sdi supports. 7.4.2 sdi in vs1002 native modes (new mode) in vs1002 native modes (sm newmode is 1), byte synchronization is achieved by xdcs. the state of xdcs may not change while a data byte transfer is in progress. to always maintain data synchronization even if there may be glitches in the boards using VS1033, it is recommended to turn xdcs every now and then, for instance once after every ?ash data block or a few kilobytes, just to keep sure the host and VS1033 are in sync. if sm sdishare is 1, the xdcs signal is internally generated by inverting the xcs input. for new designs, using vs1002 native modes are recommended. version 0.6, 2005-01-05 18 vlsi solution y
VS1033a preliminary VS1033 a 7. spi buses 7.4.3 sdi in vs1001 compatibility mode figure 4: bsync signal - one byte transfer. when VS1033 is running in vs1001 compatibility mode, a bsync signal must be generated to ensure correct bit-alignment of the input bitstream. the ?rst dclk sampling edge (rising or falling, depending on selected polarity), during which the bsync is high, marks the ?rst bit of a byte (lsb, if lsb-?rst order is used, msb, if msb-?rst order is used). if bsync is 1 when the last bit is received, the receiver stays active and next 8 bits are also received. figure 5: bsync signal - two byte transfer. 7.4.4 passive sdi mode if sm newmode is 0 and sm sdishare is 1, the operation is otherwise like the vs1001 compat- ibility mode, but bits are only received while the bsync signal is 1. rising edge of bsync is still used for synchronization. 7.5 serial protocol for serial command interface (sci) 7.5.1 general the serial bus protocol for the serial command interface sci (chapter 8.5) consists of an instruction byte, address byte and one 16-bit data word. each read or write operation can read or write a single register. data bits are read at the rising edge, so the user should update data at the falling edge. bytes are always send msb ?rst. xcs should be low for the full duration of the operation, but you can have pauses between bits if needed. the operation is speci?ed by an 8-bit instruction opcode. the supported instructions are read and write. see table below. instruction name opcode operation read 0b0000 0011 read data write 0b0000 0010 write data note: VS1033 sets dreq low after each sci operation. the duration depends on the operation. it is not allowed to start a new sci/sdi operation before dreq is high again. version 0.6, 2005-01-05 19 vlsi solution y bsyncsdata dclk d7 d6 d5 d4 d3 d2 d1 d0 bsync sdata dclk d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
VS1033a preliminary VS1033 a 7. spi buses 7.5.2 sci read figure 6: sci word read VS1033 registers are read from using the following sequence, as shown in figure 6. first, xcs line is pulled low to select the device. then the read opcode (0x3) is transmitted via the si line followed by an 8-bit word address. after the address has been read in, any further data on si is ignored by the chip. the 16-bit data corresponding to the received address will be shifted out onto the so line. xcs should be driven high after data has been shifted out. dreq is driven low for a short while when in a read operation by the chip. this is a very short time and doesnt require special user attention. 7.5.3 sci write figure 7: sci word write VS1033 registers are written from using the following sequence, as shown in figure 7. first, xcs line is pulled low to select the device. then the write opcode (0x2) is transmitted via the si line followed by an 8-bit word address. version 0.6, 2005-01-05 20 vlsi solution y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 30 31 14 15 16 17 0 0 0 0 0 0 1 1 0 0 0 0 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 1 0 x instruction (read) address data out xcssck si so don't care don't care dreq execution 0 1 2 3 4 5 6 7 8 9 10 11 12 13 30 31 14 15 16 17 0 0 0 0 0 0 1 0 0 0 0 3 2 1 0 1 0 x address xcssck si 15 14 data out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 so 0 0 0 0 x 0 instruction (write) dreq execution
VS1033a preliminary VS1033 a 7. spi buses after the word has been shifted in and the last clock has been sent, xcs should be pulled high to end the write sequence. after the last bit has been sent, dreq is driven low for the duration of the register update, marked exe- cution in the ?gure. the time varies depending on the register and its contents (see table in chapter 8.6 for details). if the maximum time is longer than what it takes from the microcontroller to feed the next sci command or sdi byte, it is not allowed to ?nish a new sci/sdi operation before dreq has risen up again. 7.6 spi timing diagram figure 8: spi timing diagram. symbol min max unit txcss 5 ns tsu -26 ns th 2 clki cycles tz 0 ns twl 2 clki cycles twh 2 clki cycles tv 2 (+ 25ns 1 ) clki cycles txcsh -26 ns txcs 2 clki cycles tdis 10 ns 1 25ns is when pin loaded with 100pf capacitance. the time is shorter with lower capacitance. note: as twl and twh, as well as th require at least 2 clock cycles, the maximum speed for the spi bus that can easily be used is 1/6 of VS1033s internal clock speed clki. slightly higher speed can be achieved with very careful timing tuning. for details, see application notes for vs10xx. note: although the timing is derived from the internal clock clki, the system always starts up in 1 : 0 mode, thus clki = xtali. note: negative numbers mean that the signal can change in different order from what is shown in the diagram. version 0.6, 2005-01-05 21 vlsi solution y xcssck si so 0 1 15 14 16 txcss txcsh twl twh th tsu tv tz tdis txcs 30 31
VS1033a preliminary VS1033 a 7. spi buses 7.7 spi examples with sm sdinew and sm sdishared set 7.7.1 two sci writes figure 9: two sci operations. figure 9 shows two consecutive sci operations. note that xcs must be raised to inactive state between the writes. also dreq must be respected as shown in the ?gure. 7.7.2 two sdi bytes figure 10: two sdi bytes. sdi data is synchronized with a raising edge of xcs as shown in figure 10. however, every byte doesnt need separate synchronization. version 0.6, 2005-01-05 22 vlsi solution y 0 1 2 3 30 31 1 0 1 0 0 0 0 0 0 0 x x xcs scksi 2 32 33 61 62 63 sci write 1 sci write 2 dreq dreq up before finishing next sci write 1 2 3 xcs scksi 7 6 5 4 3 1 0 7 6 5 2 1 0 x sdi byte 1 sdi byte 2 0 6 7 8 9 13 14 15 dreq
VS1033a preliminary VS1033 a 7. spi buses 7.7.3 sci operation in middle of two sdi bytes figure 11: two sdi bytes separated by an sci operation. figure 11 shows how an sci operation is embedded in between sdi operations. xcs edges are used to synchronize both sdi and sci. remember to respect dreq as shown in the ?gure. version 0.6, 2005-01-05 23 0 1 xcs scksi 7 7 6 5 1 0 0 0 7 6 5 1 0 sdi byte sci operation sdi byte 8 9 39 40 41 46 47 x dreq high before end of next transfer vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8 functional description 8.1 main features VS1033 is based on a proprietary digital signal processor, vs dsp. it contains all the code and data memory needed for mp3, aac, wma and wav pcm + adpcm audio decoding, midi synthesizer, together with serial interfaces, a multirate stereo audio dac and analog output ampli?ers and ?lters. also adpcm audio encoding is supported using a microphone ampli?er and a/d converter. a uart is provided for debugging purposes. 8.2 supported audio codecs conventions mark description + format is supported - format exists but is not supported format doesnt exist 8.2.1 supported mp3 (mpeg layer iii) formats mpeg 1.0 1 : samplerate / hz bitrate / kbit/s 32 40 48 56 64 80 96 112 128 160 192 224 256 320 48000 + + + + + + + + + + + + + + 44100 + + + + + + + + + + + + + + 32000 + + + + + + + + + + + + + + mpeg 2.0 1 : samplerate / hz bitrate / kbit/s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24000 + + + + + + + + + + + + + + 22050 + + + + + + + + + + + + + + 16000 + + + + + + + + + + + + + + mpeg 2.5 1 : samplerate / hz bitrate / kbit/s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 12000 + + + + + + + + + + + + + + 11025 + + + + + + + + + + + + + + 8000 + + + + + + + + + + + + + + 1 also all variable bitrate (vbr) formats are supported. version 0.6, 2005-01-05 24 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.2.2 supported mp1 (mpeg layer i) formats note: layer i / ii decoding must be speci?cally enabled from sci mode register. mpeg 1.0: samplerate / hz bitrate / kbit/s 32 64 96 128 160 192 224 256 288 320 352 384 416 448 48000 + + + + + + + + + + + + + + 44100 + + + + + + + + + + + + + + 32000 + + + + + + + + + + + + + + mpeg 2.0: samplerate / hz bitrate / kbit/s 32 48 56 64 80 96 112 128 144 160 176 192 224 256 24000 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 22050 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16000 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8.2.3 supported mp2 (mpeg layer ii) formats note: layer i / ii decoding must be speci?cally enabled from sci mode register. mpeg 1.0: samplerate / hz bitrate / kbit/s 32 48 56 64 80 96 112 128 160 192 224 256 320 384 48000 + + + + + + + + + + + + + + 44100 + + + + + + + + + + + + + + 32000 + + + + + + + + + + + + + + mpeg 2.0: samplerate / hz bitrate / kbit/s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24000 + + + + + + + + + + + + + + 22050 + + + + + + + + + + + + + + 16000 + + + + + + + + + + + + + + version 0.6, 2005-01-05 25 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.2.4 supported aac (iso/iec 13818-7) formats VS1033 decodes mpeg2-aac-lc-2.0.0.0 and mpeg4-aac-lc-2.0.0.0 streams. this means that the low complexity pro?le with maximum of two channels can be decoded. if a stream contains more than one element and/or element type, you can select which one to decode from the 16 single-channel, 16 channel-pair, and 16 low-frequency elements. the default is to select the ?rst one that appears in the stream. dynamic range control (drc) is supported and can be controlled by the user to limit or enhance the dynamic range of the material that has drc information. both sine window and kaiser-bessel-derived window are supported. for mpeg4 pseudo-random noise substitution (pns) is supported. short frames (120 and 960 samples) are not supported. for aac the streaming adts format is recommended. this format allows easy rewind and fast forward because resynchronization is easily possible. in addition to adts (.aac), mpeg2 adif (.aac) and mpeg4 audio (.mp4 / .m4a) ?les are played, but these formats are less suitable for rewind and fast forward operations. you can still implement these features by using the safe jump points table and seek mechanism provided, or using slightly less robust but much easier automatic resync mechanism (see section 9.9). note: to be able to play the .mp4 and .m4a ?les, the mdat chunk must be the last chunk in the ?le. aac 12 : samplerate / hz maximum bitrate kbit/s - for 2 channels 96 132 144 192 264 288 384 529 576 48000 + + + + + + + + + 44100 + + + + + + + + 32000 + + + + + + + 24000 + + + + + + 22050 + + + + + 16000 + + + + 12000 + + + 11025 + + 8000 + 1 64000 hz, 88200 hz, and 96000 hz aac ?les are played but with wrong speed. 2 also all variable bitrate (vbr) formats are supported. note that the table gives the maximum bitrate allowed for two channels for a speci?c sample rate as de?ned by the aac speci?cation. the decoder does not actually have a lower or upper limit. version 0.6, 2005-01-05 26 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.2.5 supported wma formats windows media audio codec versions 2, 7, 8, and 9 are supported. all wma pro?les (l1, l2, and l3) are supported. previously streams were separated into classes 1, 2a, 2b, and 3. the decoder has passed microsofts conformance testing program. wma 4.0 / 4.1: samplerate bitrate / kbit/s / hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192 8000 + + + + 11025 + + 16000 + + + + 22050 + + + + 32000 + + + + + + 44100 + + + + + + + 48000 + + wma 7: samplerate bitrate / kbit/s / hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192 8000 + + + + 11025 + + 16000 + + + + 22050 + + + + 32000 + + + + 44100 + + + + + + + + 48000 + + wma 8: samplerate bitrate / kbit/s / hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192 8000 + + + + 11025 + + 16000 + + + + 22050 + + + + 32000 + + + + 44100 + + + + + + + + 48000 + + + wma 9: samplerate bitrate / kbit/s / hz 5 6 8 10 12 16 20 22 32 40 48 64 80 96 128 160 192 256 320 8000 + + + + 11025 + + 16000 + + + + 22050 + + + + 32000 + + + + 44100 + + + + + + + + + + + 48000 + + + + + in addition to these expected wma decoding pro?les, all other bitrate and samplerate combinations are supported, including variable bitrate wma streams. note that wma does not consume the bitstream as evenly as mp3, so you need a higher peak transfer capability for clean playback at the same bitrate. version 0.6, 2005-01-05 27 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.2.6 supported riff wav formats the most common riff wav subformats are supported. format name supported comments 0x01 pcm + 16 and 8 bits, any sample rate 48 khz 0x02 adpcm - 0x03 ieee float - 0x06 alaw - 0x07 mulaw - 0x10 oki adpcm - 0x11 ima adpcm + any sample rate 48 khz 0x15 digistd - 0x16 digifix - 0x30 dolby ac2 - 0x31 gsm610 - 0x3b rockwell adpcm - 0x3c rockwell digitalk - 0x40 g721 adpcm - 0x41 g728 celp - 0x50 mpeg - 0x55 mpeglayer3 + for supported mp3 modes, see chapter 8.2.1 0x64 g726 adpcm - 0x65 g722 adpcm - version 0.6, 2005-01-05 28 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.2.7 supported midi formats general midi and sp-midi format 0 ?les are played. format 1 and 2 ?les must be converted to format 0 by the user. the maximum simultaneous polyphony is 40. actual polyphony depends on the internal clock rate (which is user-selectable), the instruments used, whether the reverb effect is enabled, and the possible global postprocessing effects enabled, such as bass and treble enhancers. the polyphony restriction algorithm makes use of the sp-midi mip table, if present. 36.86 mhz ( 3 : 0 input clock) achieves 16-26 simultaneous sustained notes. the instantaneous amount of notes can be larger. 36 mhz is a fair compromise between power consumption and quality, but higher clocks can be used to increase the polyphony. reverb effect can be controlled by the user. in addition to reverb automatic and reverb off modes, 14 different decay times can be selected. these roughly correspond to different room sizes. also, each midi song decides how much effect each instrument gets. because the reverb effect uses about 4 mhz of processing power the automatic control enables reverb only when the internal clock is at least 3 : 0 . 31 new instruments have been implemented in addition to the 36 that are available in vs1003. vs1003 melodic effect percussion piano reverse cymbal bass drum vibraphone guitar fret noise snare organ breath closed hihat guitar seashore open hihat distortion guitar bird tweet high tom bass telephone low tom violin helicopter crash cymbal 2 strings applause ride cymbal trumpet gunshot tambourine sax high conga ?ute low conga lead maracas pad claves steeldrum new in VS1033 melodic percussion slap bass 1 high mid tom synth bass 1 low mid tom synth bass 2 high ?oor tom church organ low ?oor tom guitar (nylon) crash cymbal 1 choir aahs cow bell pizzicato strings open triangle square lead mute triangle chiff lead long whistle ?fths lead short whistle bass lead side stick warm pad hand clap polysynth cabasa sweep pad low wood block wood block high wood block castanets version 0.6, 2005-01-05 29 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.3 data flow of VS1033 figure 12: data flow of VS1033. first, depending on the audio data, and provided adpcm encoding mode is not set, mp3, wma, aac, pcm wav, ima adpcm wav, or midi data is received and decoded from the sdi bus. after decoding, if sci aiaddr is non-zero, application code is executed from the address pointed to by that register. for more details, see application notes for vs10xx. then data may be sent to the bass and treble enhancer depending on the sci bass register. after that the signal is fed to the volume control unit, which also copies the data to the audio fifo. the audio fifo holds the data, which is read by the audio interrupt (chapter 10.14.1) and fed to the sample rate converter and dacs. the size of the audio fifo is 2048 stereo (2 16-bit) samples, or 8 kib. the sample rate converter converts all different sample rates to xtali/2, or 128 times the highest us- able sample rate. this removes the need for complex pll-based clocking schemes and allows almost unlimited sample rate accuracy with one ?xed input clock frequency. with a 12.288 mhz clock, the da converter operates at 128 48 khz, i.e. 6.144 mhz, and creates a stereo in-phase analog signal. the oversampled output is low-pass ?ltered by an on-chip analog ?lter. this signal is then forwarded to the earphone ampli?er. 8.4 serial data interface (sdi) the serial data interface is meant for transferring compressed mp3, wma, or aac data, wav pcm and adpcm data as well as midi data. if the input of the decoder is invalid or it is not received fast enough, analog outputs are automatically muted. also several different tests may be activated through sdi as described in chapter 9. version 0.6, 2005-01-05 30 volumecontrol audiofifo s.rate.conv.and dac r bitstreamfifo sdi l sci_vol sm_adpcm=0 2048 stereo samples bassenhancer sb_amplitude=0sb_amplitude!=0 aiaddr = 0 aiaddr != 0 userapplication st_amplitude=0st_amplitude!=0 trebleenhancer mp3wav/adpcm/ wma / aac / midi decode vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.5 serial control interface (sci) the serial control interface is compatible with the spi bus speci?cation. data transfers are always 16 bits. VS1033 is controlled by writing and reading the registers of the interface. the main controls of the control interface are: 2 control of the operation mode, clock, and builtin effects 2 access to status information and header data 2 access to encoded digital data 2 uploading user programs 8.6 sci registers VS1033 sets dreq low when it detects an sci operation and restores it when it has processed the operation. the duration depends on the operation. do not start a new sci/sdi operation before dreq is high again. if dreq is low when an sci operation is performed, it also stays low after sci operation processing. sci registers, pre?x sci reg type reset time 1 abbrev[bits] description 0x0 rw 0x800 70 clki 4 mode mode control 0x1 rw 0x0c 3 40 clki status status of VS1033 0x2 rw 0 2100 clki bass built-in bass/treble enhancer 0x3 rw 0 11000 xtali 5 clockf clock freq + multiplier 0x4 rw 0 40 clki decode time decode time in seconds 0x5 rw 0 3200 clki audata misc. audio data 0x6 rw 0 80 clki wram ram write/read 0x7 rw 0 80 clki wramaddr base address for ram write/read 0x8 r 0 - hdat0 stream header data 0 0x9 r 0 - hdat1 stream header data 1 0xa rw 0 3200 clki 2 aiaddr start address of application 0xb rw 0 2100 clki vol volume control 0xc rw 0 50 clki 2 aictrl0 application control register 0 0xd rw 0 50 clki 2 aictrl1 application control register 1 0xe rw 0 50 clki 2 aictrl2 application control register 2 0xf rw 0 50 clki 2 aictrl3 application control register 3 1 this is the worst-case time that dreq stays low after writing to this register. the user may choose to skip the dreq check for those register writes that take less than 100 clock cycles to execute. 2 in addition, the cycles spent in the user application routine must be counted. 3 firmware changes the value of this register immediately to 0x48, and in less than 100 ms to 0x40. 4 when mode register write speci?es a software reset the worst-case time is 16600 xtali cycles. 5 writing to this register may force internal clock to run at 1 : 0 xtali for a while. thus it is not a good idea to send sci or sdi bits while this register update is in progress. version 0.6, 2005-01-05 31 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.6.1 sci mode (rw) sci mode is used to control the operation of VS1033 and defaults to 0x0800 (sm sdinew set). bit name function value description 0 sm diff differential 0 normal in-phase audio 1 left channel inverted 1 sm layer12 allow mpeg layers i & ii 0 no 1 yes 2 sm reset soft reset 0 no reset 1 reset 3 sm outofwav jump out of wav decoding 0 no 1 yes 4 sm pdown powerdown 0 power on 1 powerdown 5 sm tests allow sdi tests 0 not allowed 1 allowed 6 sm stream stream mode 0 no 1 yes 7 sm settozero2 set to zero 0 right 1 wrong 8 sm dact dclk active edge 0 rising 1 falling 9 sm sdiord sdi bit order 0 msb ?rst 1 msb last 10 sm sdishare share spi chip select 0 no 1 yes 11 sm sdinew vs1002 native spi modes 0 no 1 yes 12 sm adpcm adpcm recording active 0 no 1 yes 13 sm adpcm hp adpcm high-pass ?lter active 0 no 1 yes 14 sm line in adpcm recording selector 0 microphone 1 line in 15 sm clk range input clock range 0 12..13 mhz 1 24..26 mhz when sm diff is set, the player inverts the left channel output. for a stereo input this creates virtual surround, and for a mono input this creates a differential left/right signal. sm layer12 enables mpeg 1.0 and 2.0 layer i and ii decoding in addition to layer iii. if you enable layer i and layer ii decoding, you are liable for any patent issues that may arise. joint licensing of mpeg 1.0 / 2.0 layer iii does not cover all patents pertaining to layers i and ii. software reset is initiated by setting sm reset to 1. this bit is cleared automatically. if you want to stop decoding a wav, wma, or midi ?le in the middle, set sm outofwav, and send data honouring dreq until sm outofwav is cleared. sci hdat1 will also be cleared. for wma and midi it is safest to continue sending the stream, send zeroes for wav. bit sm pdown sets VS1033 into software powerdown mode. during powerdown, no audio is played and no sdi operations are performed. for best results, set sci vol to 0xffff before activating soft- ware powerdown. note that software powerdown is not nearly as power ef?cient as hardware powerdown activated with the xreset pin. if sm tests is set, sdi tests are allowed. for more details on sdi tests, look at chapter 9.10. version 0.6, 2005-01-05 32 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description sm stream activates VS1033s stream mode. in this mode, data should be sent with as even intervals as possible and preferable in blocks of less than 512 bytes, and VS1033 makes every attempt to keep its input buffer half full by changing its playback speed upto 5%. for best quality sound, the average speed error should be within 0.5%, the bitrate should not exceed 160 kbit/s and vbr should not be used. for details, see application notes for vs10xx. this mode only works with mp3 and wav ?les. sm dact de?nes the active edge of data clock for sdi. when 0, data is read at the rising edge, when 1, data is read at the falling edge. when sm sdiord is clear, bytes on sdi are sent msb ?rst. by setting sm sdiord, the user may reverse the bit order for sdi, i.e. bit 0 is received ?rst and bit 7 last. bytes are, however, still sent in the default order. this register bit has no effect on the sci bus. setting sm sdishare makes sci and sdi share the same chip select, as explained in chapter 7.2, if also sm sdinew is set. setting sm sdinew will activate vs1002 native serial modes as described in chapters 7.2.1 and 7.4.2. note, that this bit is set as a default when VS1033 is started up. by activating sm adpcm and sm reset at the same time, the user will activate ima adpcm record- ing mode. more information is available in the application notes for vs10xx. if sm adpcm hp is set at the same time as sm adpcm and sm reset, adpcm mode will start with a high-pass ?lter. this may help intelligibility of speech when there is lots of background noise. the difference created to the adpcm encoder frequency response is as shown in figure 13. figure 13: adpcm frequency responses with 8 khz sample rate. sm line in is used to select the input for adpcm recording. if 0, microphone input pins micp and micn are used; if 1, linein is used. sm clk range activates a clock divider in the xtal input. when sm clk range is set, from the chips point of view e.g. 24 mhz becomes 12 mhz. sm clk range should be set as soon as possible after a chip reset. version 0.6, 2005-01-05 33 0 500 1000 1500 2000 2500 3000 3500 4000 ?20 ?15 ?10 ?5 0 5 vs1023 ad converter with and without hp filter frequency / hz amplitude / db no high?passhigh?pass vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.6.2 sci status (rw) sci status contains information on the current status of VS1033 and lets the user shutdown the chip without audio glitches. name bits description ss ver 6:4 version ss apdown2 3 analog driver powerdown ss apdown1 2 analog internal powerdown ss avol 1:0 analog volume control ss ver is 0 for vs1001, 1 for vs1011, 2 for vs1002, 3 for vs1003, and 5 for VS1033. ss apdown2 controls analog driver powerdown. normally this bit is controlled by the system ?rmware. however, if the user wants to powerdown VS1033 with a minimum power-off transient, turn this bit to 1, then wait for at least a few milliseconds before activating reset. ss apdown1 controls internal analog powerdown. this bit is meant to be used by the system ?rmware only. ss avol is the analog volume control: 0 = -0 db, 1 = -6 db, 3 = -12 db. this register is meant to be used automatically by the system ?rmware only. 8.6.3 sci bass (rw) name bits description st amplitude 15:12 treble control in 1.5 db steps (-8..7, 0 = off) st freqlimit 11:8 lower limit frequency in 1000 hz steps (0..15) sb amplitude 7:4 bass enhancement in 1 db steps (0..15, 0 = off) sb freqlimit 3:0 lower limit frequency in 10 hz steps (2..15) the bass enhancer vsbe is a powerful bass boosting dsp algorithm, which tries to take the most out of the users earphones without causing clipping. vsbe is activated when sb amplitude is non-zero. sb amplitude should be set to the users preferences, and sb freqlimit to roughly 1.5 times the lowest frequency the users audio system can reproduce. for example setting sci bass to 0x00f6 will have 15 db enhancement below 60 hz. note: because vsbe tries to avoid clipping, it gives the best bass boost with dynamical music material, or when the playback volume is not set to maximum. it also does not create bass: the source material must have some bass to begin with. treble control vstc is activated when st amplitude is non-zero. for example setting sci bass to 0x7a00 will have 10.5 db treble enhancement at and above 10 khz. bass enhancer uses about 2.1 mips and treble control 1.2 mips at 44100 hz sample rate. both can be on simultaneously. version 0.6, 2005-01-05 34 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.6.4 sci clockf (rw) the operation of sci clockf is different in vs1003 and VS1033 than in vs10x1 and vs1002. for general applications with 12.288 mhz clock use 0x9000 for 3 : 0 :: 4 : 0 , or 0xa800 for 3 : 5 :: 4 : 0 . sci clockf bits name bits description sc mult 15:13 clock multiplier sc add 12:11 allowed multiplier addition sc freq 10: 0 clock frequency sc mult activates the built-in clock multiplier. this will multiply xtali to create a higher clki. the values are as follows: sc mult mask clki 0 0x0000 xtali 1 0x2000 xtali 1 : 5 2 0x4000 xtali 2 : 0 3 0x6000 xtali 2 : 5 4 0x8000 xtali 3 : 0 5 0xa000 xtali 3 : 5 6 0xc000 xtali 4 : 0 7 0xe000 xtali 4 : 5 sc add tells, how much the decoder ?rmware is allowed to add to the multiplier speci?ed by sc mult if more cycles are temporarily needed to decode a wma stream. the values are: sc add mask multiplier addition 0 0x0000 no modi?cation is allowed 1 0x0800 0.5 2 0x1000 1.0 3 0x1800 1.5 sc freq is used to tell if the input clock xtali is running at something else than 12.288 mhz. xtali is set in 4 khz steps. the formula for calculating the correct value for this register is xt ali ? 8000000 4000 (xtali is in hz). note: the default value 0 is assumed to mean xtali=12.288 mhz. note: because maximum sample rate is xt ali 256 , all sample rates are not available if xtali < 12 : 288 mhz. note: automatic clock change can only happen when decoding wma ?les. automatic clock change is done one 0 : 5 at a time. this does not cause a drop to 1 : 0 clock and you can use the same sci and sdi clock throughout the wma ?le. example: if sci clockf is 0x9be8, sc mult = 4, sc add = 3 and sc freq = 0x3e8 = 1000. this means that xtali = 1000 4000+8000000 = 12 mhz. the clock multiplier is set to 3 : 0 xtali = 36 mhz, and the maximum allowed multiplier that the ?rmware may automatically choose to use is (3 : 0 + 1 : 5) xtali = 54 mhz. version 0.6, 2005-01-05 35 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.6.5 sci decode time (rw) when decoding correct data, current decoded time is shown in this register in full seconds. the user may change the value of this register. in that case the new value should be written twice. sci decode time is reset at every software reset and also when wav (pcm or ima adpcm), aac, wma, or midi decoding starts or ends. 8.6.6 sci audata (rw) when decoding correct data, the current sample rate and number of channels can be found in bits 15:1 and 0 of sci audata, respectively. bits 15:1 contain the sample rate divided by two, and bit 0 is 0 for mono data and 1 for stereo. writing to sci audata will change the sample rate directly. example: 44100 hz stereo data reads as 0xac45 (44101). example: 11025 hz mono data reads as 0x2b10 (11024). example: writing 0xac80 sets sample rate to 44160 hz, stereo mode does not change. 8.6.7 sci wram (rw) sci wram is used to upload application programs and data to instruction and data rams. the start address must be initialized by writing to sci wramaddr prior to the ?rst write/read of sci wram. as 16 bits of data can be transferred with one sci wram write/read, and the instruction word is 32 bits long, two consecutive writes/reads are needed for each instruction word. the byte order is big-endian (i.e. most signi?cant words ?rst). after each full-word write/read, the internal pointer is autoincremented. 8.6.8 sci wramaddr (w) sci wramaddr is used to set the program address for following sci wram writes/reads. address offset of 0 is used for x, 0x4000 for y, and 0x8000 for instruction memory. peripheral registers can also be accessed. sm wramaddr dest. addr. bits/ description start. . . end start. . . end word 0x1800. . . 0x187f 0x1800. . . 0x187f 16 x data ram 0x5800. . . 0x587f 0x1800. . . 0x187f 16 y data ram 0x8030. . . 0x84ff 0x0030. . . 0x04ff 32 instruction ram 0xc000. . . 0xffff 0xc000. . . 0xffff 16 i/o only user areas in x, y, and instruction memory are listed above. other areas can be accessed, but should not be written to unless otherwise speci?ed. version 0.6, 2005-01-05 36 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description 8.6.9 sci hdat0 and sci hdat1 (r) for wav ?les, sci hdat1 contains 0x7665 (ve). sci hdat0 contains the data rate in double word increments for all supported riff wave formats: mono and stereo 8-bit or 16-bit pcm, mono and stereo ima adpcm. to get the byte rate of the ?le, multiply the value by 4. to get the bit rate of the ?le, multiply the value by 32. note: usage of sci hdat0 with wav ?les has changed from vs1003. for aac adts streams, sci hdat1 contains 0x4154 (at). for aac adif ?les, sci hdat1 con- tains 0x4144 (ad). for aac .mp4 / .m4a ?les, sci hdat1 contains 0x4d34 (m4). sci hdat0 contains the average data rate in bytes per second. to get the bit rate of the ?le, multiply the value by 8. for wma ?les, sci hdat1 contains 0x574d (wm) and sci hdat0 contains the data rate measured in bytes per second. to get the bit rate of the ?le, multiply the value by 8. for midi ?les, sci hdat1 contains 0x4d54 (mt) and sci hdat0 contains the average data rate in bytes per second. to get the bit rate of the ?le, multiply the value by 8. note: usage of sci hdat0 with midi has changed from vs1003. for mp3 ?les, sci hdat1 is between 0xffe0 and 0xffff. sci hdat1 / 0 contain the following: bit function value explanation hdat1[15:5] syncword 2047 stream valid hdat1[4:3] id 3 iso 11172-3 mpg 1.0 2 iso 13818-3 mpg 2.0 (1/2-rate) 1 mpg 2.5 (1/4-rate) 0 mpg 2.5 (1/4-rate) hdat1[2:1] layer 3 i 2 ii 1 iii 0 reserved hdat1[0] protect bit 1 no crc 0 crc protected hdat0[15:12] bitrate see bitrate table hdat0[11:10] sample rate 3 reserved 2 32/16/ 8 khz 1 48/24/12 khz 0 44/22/11 khz hdat0[9] pad bit 1 additional slot 0 normal frame hdat0[8] private bit not de?ned hdat0[7:6] mode 3 mono 2 dual channel 1 joint stereo 0 stereo hdat0[5:4] extension see iso 11172-3 hdat0[3] copyright 1 copyrighted 0 free hdat0[2] original 1 original 0 copy hdat0[1:0] emphasis 3 ccitt j.17 2 reserved 1 50/15 microsec 0 none version 0.6, 2005-01-05 37 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description when read, sci hdat0 and sci hdat1 contain header information that is extracted from mp3 stream currently being decoded. after reset both registers are cleared, indicating no data has been found yet. the sample rate ?eld in sci hdat0 is interpreted according to the following table: sample rate id=3 id=2 id=0,1 3 - - - 2 32000 16000 8000 1 48000 24000 12000 0 44100 22050 11025 the bitrate ?eld in hdat0 is read according to the following table. notice that for variable bitrate stream the value changes constantly. layer i layer ii layer iii bitrate id=3 id=0,1,2 id=3 id=0,1,2 id=3 id=0,1,2 kbit/s kbit/s kbit/s 15 forbidden forbidden forbidden forbidden forbidden forbidden 14 448 256 384 160 320 160 13 416 224 320 144 256 144 12 384 192 256 128 224 128 11 352 176 224 112 192 112 10 320 160 192 96 160 96 9 288 144 160 80 128 80 8 256 128 128 64 112 64 7 224 112 112 56 96 56 6 192 96 96 48 80 48 5 160 80 80 40 64 40 4 128 64 64 32 56 32 3 96 56 56 24 48 24 2 64 48 48 16 40 16 1 32 32 32 8 32 8 0 - - - - - - 8.6.10 sci aiaddr (rw) sci aiaddr indicates the start address of the application code written earlier with sci wramaddr and sci wram registers. if no application code is used, this register should not be initialized, or it should be initialized to zero. for more details, see application notes for vs10xx. 8.6.11 sci vol (rw) sci vol is a volume control for the player hardware. for each channel, a value in the range of 0..254 may be de?ned to set its attenuation from the maximum volume level (in 0.5 db steps). the left channel version 0.6, 2005-01-05 38 vlsi solution y
VS1033a preliminary VS1033 a 8. functional description value is then multiplied by 256 and the values are added. thus, maximum volume is 0 and total silence is 0xfefe. example: for a volume of -2.0 db for the left channel and -3.5 db for the right channel: (4*256) + 7 = 0x407. note, that at startup volume is set to full volume. resetting the software does not reset the volume setting. note: setting sci vol to 0xffff will activate analog powerdown mode. 8.6.12 sci aictrl[x] (rw) sci aictrl[x] registers ( x=[0 .. 3] ) can be used to access the users application program. version 0.6, 2005-01-05 39 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9 operation 9.1 clocking VS1033 operates on a single, nominally 12.288 mhz fundamental frequency master clock. this clock can be generated by external circuitry (connected to pin xtali) or by the internal clock chrystal interface (pins xtali and xtalo). VS1033 can also use 24..26 mhz clocks when sm clk range is set to 1. from the chips point of view the input clock is then 12..23 mhz. 9.2 hardware reset when the xreset -signal is driven low, VS1033 is reset and all the control registers and internal states are set to the initial values. xreset-signal is asynchronous to any external clock. the reset mode doubles as a full-powerdown mode, where both digital and analog parts of VS1033 are in minimum power consumption stage, and where clocks are stopped. also xtalo is grounded. after a hardware reset (or at power-up) dreq will stay down for at least 16600 clock cycles, which means an approximate 1.35 ms delay if VS1033 is run at 12.288 mhz. after this the user should set such basic software registers as sci mode, sci bass, sci clockf, and sci vol before starting decoding. see section 8.6 for details. if the input clock is 24..26 mhz, sm clk range should be set as soon as possible after a chip reset. internal clock can be multiplied with a pll. supported multipliers through the sci clockf register are 1 : 0 : : : 4 : 5 the input clock. reset value for internal clock multiplier is 1 : 0 . if typical values are wanted, the internal clock multiplier needs to be set to 3 : 0 after reset. wait until dreq rises, then write value 0x9800 to sci clockf (register 3). see section 8.6.4 for details. 9.3 software reset in some cases the decoder software has to be reset. this is done by activating bit 2 in sci mode register (chapter 8.6.1). then wait for at least 2 1 s, then look at dreq. dreq will stay down for at least 16600 clock cycles, which means an approximate 1.35 ms delay if VS1033 is run at 12.288 mhz. after dreq is up, you may continue playback as usual. if you want to make sure VS1033 doesnt cut the ending of low-bitrate data streams and you want to do a software reset, it is recommended to feed 2048 zeros (honoring dreq) to the sdi bus after the ?le and before the reset. this is especially important for midi ?les. if you want to interrupt the playing of a wav, aac, wma, or midi ?le in the middle, set sm outofwav in the mode register, and wait until sci hdat1 is cleared (with a two-second timeout) before continu- ing with a software reset. mp3 can be interrupted without sm outofwav by just sending zero bytes, because it is a stream format. version 0.6, 2005-01-05 40 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.4 adpcm recording this chapter explains how to create riff/wav ?le with ima adpcm format. this is a widely sup- ported adpcm format and many pc audio playback programs can play it. ima adpcm recording gives roughly a compression ratio of 4:1 compared to linear, 16-bit audio. this makes it possible to record 8 khz audio at 32.44 kbit/s. 9.4.1 activating adpcm mode ima adpcm recording mode is activated by setting bits sm reset and sm adpcm in sci mode. optionally a high-pass-?lter can be enabled for 8 khz sample rate by also setting sm adpcm hp at the same time. line input is used instead of mic if sm line in is set. before activating adpcm recording, user must write a clock divider value to sci aictrl0 and gain to sci aictrl1. the differences of using sm adpcm hp are presented in ?gure 13 (page 33). as a general rule, audio will be fuller and closer to original if sm adpcm hp is not used. however, speech may be more intelligible with the high-pass ?lter active. use the ?lter only with 8 khz sample rate. before activating adpcm recording, user should write a clock divider value to sci aictrl0. the sampling frequency is calculated from the following formula: f s = f c 256 d , where f c is the internal clock (clki) and d is the divider value in sci aictrl0. the lowest valid value for d is 4. if sci aictrl0 contains 0, the default divider value 12 is used. examples: f c = 2 : 0 12 : 288 mhz, d = 12 . now f s = 2 : 0 12288000 256 12 = 8000 hz. f c = 2 : 5 14 : 745 mhz, d = 18 . now f s = 2 : 5 14745000 256 18 = 8000 hz. f c = 2 : 5 13 mhz, d = 16 . now f s = 2 : 5 13000000 256 16 = 7935 hz. also, before activating adpcm mode, the user has to set linear recording gain control to register sci aictrl1. 1024 is equal to digital gain 1, 512 is equal to digital gain 0.5 and so on. if the user wants to use automatic gain control (agc), sci aictrl1 should be set to 0. typical speech appli- cations usually are better off using agc, as this takes care of relatively uniform speech loudness in recordings. 9.4.2 reading ima adpcm data after ima adpcm recording has been activated, registers sci hdat0 and sci hdat1 have new functions. the ima adpcm sample buffer is 1024 16-bit words. the ?ll status of the buffer can be read from sci hdat1. if sci hdat1 is greater than 0, you can read as many 16-bit words from sci hdat0. if the data is not read fast enough, the buffer over?ows and returns to empty state. note: if sci hdat1 ? 896 , it may be better to wait for the buffer to over?ow and clear before reading samples. that way you may avoid buffer aliasing. each ima adpcm block is 128 words, i.e. 256 bytes. if you wish to interrupt reading data and possibly continue later, please stop at a 128-word boundary. this way whole blocks are skipped and the encoded version 0.6, 2005-01-05 41 vlsi solution y
VS1033a preliminary VS1033 a 9. operation stream stays valid. 9.4.3 adding a riff header to make your ima adpcm ?le a riff / wav ?le, you have to add a header before the actual data. note that 2- and 4-byte values are little-endian (lowest byte ?rst) in this format: file offset field name size bytes description 0 chunkid 4 "riff" 4 chunksize 4 f0 f1 f2 f3 file size - 8 8 format 4 "wave" 12 subchunk1id 4 "fmt " 16 subchunk1size 4 0x14 0x0 0x0 0x0 20 20 audioformat 2 0x11 0x0 0x11 for ima adpcm 22 numofchannels 2 0x1 0x0 mono sound 24 samplerate 4 r0 r1 r2 r3 0x1f40 for 8 khz 28 byterate 4 b0 b1 b2 b3 0xfd7 for 8 khz 32 blockalign 2 0x0 0x1 0x100 34 bitspersample 2 0x4 0x0 4-bit adpcm 36 byteextradata 2 0x2 0x0 2 38 extradata 2 0xf9 0x1 samples per block (505) 40 subchunk2id 4 "fact" 44 subchunk2size 4 0x4 0x0 0x0 0x0 4 48 numofsamples 4 s0 s1 s2 s3 52 subchunk3id 4 "data" 56 subchunk3size 4 d0 d1 d2 d3 file size - 60 60 block1sample 2 16-bit linear ?rst sample 62 block1step 2 adpcm state 64 block1data 252 504 4-bit adpcm samples 316 . . . more adpcm data blocks if we have n audio blocks, the values in the table are as follows: f = n 256 + 52 r = f s (see chapter 9.4.1 to see how to calculate f s ) b = f s 256 505 s = n 505 . d = n 256 if you know beforehand how much you are going to record, you may ?ll in the complete header before any actual data. however, if you dont know how much you are going to record, you have to ?ll in the header size datas f , s and d after ?nishing recording. 16-bit adpcm values that are read from sci hdat0 are to be interpreted as big-endian values. in other words, the high 8 bits of sci hdat0 should be written as the ?rst byte to a ?le, then the low 8 bits. note that this is contrary to the default operation of some 16-bit microcontrollers, and you may have to take extra care to do this right. a way to see if you have written the ?le in the right way is to check bytes 2 and 3 (the ?rst byte counts as byte 0) of each 256-byte block. byte 3 should always be zero. version 0.6, 2005-01-05 42 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.4.4 playing adpcm data in order to play back your ima adpcm recordings, you have to have a ?le with a header as described in chapter 9.4.3. if this is the case, all you need to do is to provide the adpcm ?le through sdi as you would with any audio ?le. 9.4.5 sample rate considerations vs10xx chips that support ima adpcm playback are capable of playing back adpcm ?les with any sample rate. however, some other programs may expect ima adpcm ?les to have some exact sample rates, like 8000 or 11025 hz. also, some programs or systems do not support sample rates below 8000 hz. however, if you dont have an appropriate clock, you may not be able to get an exact 8 khz sample rate. if you have a 12 mhz clock, the closest sample rate you can get with 2 : 0 12 mhz and d = 12 is f s = 7812 : 5 hz . because the frequency error is only 2.4%, it may be best to set f s = 8000 hz to the header if the same ?le is also to be played back with an pc. this causes the sample to be played back a little faster (one minute is played in 59 seconds). note, however, that unless absolutely necessary, sample rates should not be tweaked in the way described here. if you want better quality with the expense of increased data rate, you can use higher sample rates, for example 16 khz. 9.4.6 example code the following code initializes ima adpcm encoding on vs1003b/vs1023 and shows how to read the data. const unsigned char header[] = { 0x52, 0x49, 0x46, 0x46, 0x1c, 0x10, 0x00, 0x00, 0x57, 0x41, 0x56, 0x45, 0x66, 0x6d, 0x74, 0x20, /*|riff....wavefmt |*/ 0x14, 0x00, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00, 0x40, 0x1f, 0x00, 0x00, 0x75, 0x12, 0x00, 0x00, /*|........@......|*/ 0x00, 0x01, 0x04, 0x00, 0x02, 0x00, 0xf9, 0x01, 0x66, 0x61, 0x63, 0x74, 0x04, 0x00, 0x00, 0x00, /*|.......fact....|*/ 0x5c, 0x1f, 0x00, 0x00, 0x64, 0x61, 0x74, 0x61, 0xe8, 0x0f, 0x00, 0x00 }; unsigned char db[512]; /* data buffer for saving to disk */ version 0.6, 2005-01-05 43 vlsi solution y
VS1033a preliminary VS1033 a 9. operation void recordadpcm1003(void) { /* vs1003b/vs1023 */ u_int16 w = 0, idx = 0; ... /* check and locate free space on disk */ setmp3vol(0x1414); /* recording monitor volume */ writemp3spireg(sci_bass, 0); /* bass/treble disabled */ writemp3spireg(sci_clockf, 0x4430); /* 2.0x 12.288mhz */ wait(100); writemp3spireg(sci_aictrl0, 12); /* div -> 12=8khz 8=12khz 6=16khz */ wait(100); writemp3spireg(sci_aictrl1, 0); /* auto gain */ wait(100); if (line_in) { writemp3spireg(sci_mode, 0x5804); /* normal sw reset + other bits */ } else { writemp3spireg(sci_mode, 0x1804); /* normal sw reset + other bits */ } for (idx=0; idx < sizeof(header); idx++) { /* save header first */ db[idx] = header[idx]; } /* fix rate if needed */ /*db[24] = rate;*/ /*db[25] = rate>>8;*/ /* record loop */ while (recording_on) { do { w = readmp3spireg(sci_hdat1); } while (w < 256 || w > 896); while (idx < 512) { w = readmp3spireg(sci_hdat0); /* resynchronize if ima sync is lost */ while ((idx & 255) == sizeof(header)+2 && (w & 0xff)) { do { w = readmp3spireg(sci_hdat1); } while (w < 256); w = readmp3spireg(sci_hdat0); } db[idx++] = w>>8; db[idx++] = w&0xff; } idx = 0; write_block(datasector++, db); /* write output block to disk */ } ... /* fix wav header information */ ... /* then update fat information */ resetmp3(); /* normal reset, restore default settings */ setmp3vol(vol); } version 0.6, 2005-01-05 44 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.5 spi boot if gpio0 is set with a pull-up resistor to 1 at boot time, VS1033 tries to boot from external spi memory. spi boot rede?nes the following pins: normal mode spi boot mode gpio0 xcs gpio1 clk dreq mosi gpio2 miso the memory has to be an spi bus serial eeprom with 16-bit addresses (i.e. at least 1 kib). the serial speed used by VS1033 is 245 khz with the nominal 12.288 mhz clock. the ?rst three bytes in the memory have to be 0x50, 0x26, 0x48. the exact record format is explained in the application notes for vs10xx. 9.6 play/decode this is the normal operation mode of VS1033. sdi data is decoded. decoded samples are converted to analog domain by the internal dac. if no decodable data is found, sci hdat0 and sci hdat1 are set to 0 and analog outputs are muted. when there is no input for decoding, VS1033 goes into idle mode (lower power consumption than during decoding) and actively monitors the serial data input for valid data. all different formats can be played back-to-back without software reset in-between. send at least 2052 zeros after each stream. however, using software reset between streams may still be a good idea, as it guards against broken ?les. in this case you shouldt wait for the completion of the decoding (sci hdat1 and sci hdat0 become zero) before issuing software reset. 9.7 feeding pcm data VS1033 can be used as a pcm decoder by sending a wav ?le header. if the length sent in the wav header is 0 or 0xfffffff, VS1033 will stay in pcm mode inde?nitely (or until sm outofwav has been set). 8-bit linear and 16-bit linear audio is supported in mono or stereo. version 0.6, 2005-01-05 45 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.8 extra parameters the following structure is in x memory at address 0x1940 and can be used to change some extra param- eters or get various information. the chip id is also easily available. #define parametric_version 0x0001 struct parametric { u_int32 chipid; /*1940/41 initialized at reset for your convenience */ u_int16 version; /*1942 - structure version */ u_int16 midiconfig; /*1943 */ u_int16 config1; /*1944 */ u_int16 config2; /*1945 configs are not cleared between files */ u_int32 jumppoints[16]; /*1946..65 file byte offsets */ u_int16 latestjump; /*1966 index to lastly updated jumppoint */ s_int16 seek1; /*1967 file data inserted/removed bytes -32768..32767*/ s_int16 seek2; /*1968 file data inserted/removed kb -32768..32767*/ s_int16 resync; /*1969 > 0 for automatic m4a, adif, wma resyncs */ union { struct { u_int32 curpacketsize; u_int32 packetsize; } wma; struct { u_int16 scefoundmask; /* sces found since last clear */ u_int16 cpefoundmask; /* cpes found since last clear */ u_int16 lfefoundmask; /* lfes found since last clear */ u_int16 playselect; /* 0 = first any, initialized at aac init */ s_int16 dyncompress; /* -8192=1.0, initialized at aac init */ s_int16 dynboost; /* 8192=1.0, initialized at aac init */ } aac; struct { u_int32 bytesleft; } midi; } i; }; notice that reading two-word variables through the sci wramaddr and sci wram interface is not protected in any way. the variable can be updated between the read of the low and high parts. the problem arises when both the low and high parts change values. to determine if the value is correct, you should read the value twice and compare the results. the following example shows what happens when bytesleft is decreased from 0x10000 to 0xffff and the update happens between low and high part reads or after high part read. read invalid address value 0x196a 0x0000 change after this 0x196b 0x0000 0x196a 0xffff 0x196b 0x0000 read valid address value 0x196a 0x0000 0x196b 0x0001 change after this 0x196a 0xffff 0x196b 0x0000 no update address value 0x196a 0x0000 0x196b 0x0001 0x196a 0x0000 0x196b 0x0001 you can see that in the invalid read the low part wraps from 0x0000 to 0xffff while the high part stays the same. in this case the second read gives a valid answer, otherwise always use the value of the ?rst read. the second read is needed when it is possible that the low part wraps around, changing the high part, i.e. when the low part is small. bytesleft is only decreased by one at a time, so a reread is needed only if the low part is 0. version 0.6, 2005-01-05 46 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.8.1 common parameters parameter address usage chipid 0x1940/41 fuse-programmed unique id (copy) version 0x1942 structure version C 0x0001 jumppoints[16] 0x1946-65 packet offsets for wma and aac latestjump 0x1966 index to latest jumppoint seek1 0x1967 seek amount in bytes seek2 0x1968 seek amount in kilobytes resync 0x1969 automatic resync selector the fuse-programmed id is read at startup and copied into the chipid ?eld. the version ?eld can be used to determine the layout of the rest of the structure. the version number is changed when the structure is changed. jumppoints contain 32-bit ?le offsets. each valid (non-zero) entry indicates a start of a packet for wma or start of a raw data block for aac (adif, .mp4 / .m4a). latestjump contains the index of the entry that was updated last. if you only read entry pointed to by latestjump you do not need to read the entry twice to ensure validity. jump point information can be used to implement perfect fast forward and rewind for wma and aac (adif, .mp4 / .m4a). seek1 and seek2 ?elds are used when music data is skipped or inserted. negative values mean that data has been added (for example in rewind operation), positive values mean that data has been skipped. you can use either seek1 , which gives the seek amount in bytes, or seek2 which gives the seek amount in kilobytes, or you can use both. the ?eld value is zeroed when the ?rmware has detected the seek. resync ?eld is used to force a resynchronization to the stream for wma and aac (adif, .mp4 / .m4a). this ?eld can be used to implement almost perfect fast forward and rewind for wma and aac (adif, .mp4 / .m4a). the user should set this ?eld before performing data seeks if they are not in packet or data block boundaries. the ?eld value tells how many tries are allowed before giving up. the value 32767 gives in?nite tries, in which case the user must use sm outofwav or software reset to end decoding. in every case remember to use seek1 and/or seek2 ?elds to indicate the skipped/inserted data. note: wma, adif, and .mp4 / .m4a ?les begin with a metadata section, which must be fully processed before any fast forward or rewind operation. when the ?rst jumppoint appears it is safe to perform seeks. you can also detect the start of decoding from sci decode time. 9.8.2 wma parameter address usage curpacketsize 0x196a/6b the size of the packet being processed packetsize 0x196c/6d the packet size in asf header the asf header packet size is available in packetsize . with this information and a packet start offset from jumppoints you can parse the packet headers and skip packets in asf ?les. version 0.6, 2005-01-05 47 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.8.3 aac parameter address usage scefoundmask 0x196a single channel elements found cpefoundmask 0x196b channel pair elements found lfefoundmask 0x196c low frequency elements found playselect 0x196d play element selection dyncompress 0x196e compress coef?cient for drc, -8192=1.0 dynboost 0x196f boost coef?cient for drc, 8192=1.0 playselect determines which element to decode if a stream has multiple elements. the value is set to 0 each time aac decoding starts, which causes the ?rst element that appears in the stream to be selected for decoding. other values are: 0x01 - select ?rst single channel element (sce), 0x02 - select ?rst channel pair element (cpe), 0x03 - select ?rst low frequency element (lfe), s 16 + 5 - select sce number s, p 16 + 6 - select cpe number p, l 16 + 7 - select lfe number l. when automatic selection has been performed, playselect re?ects the selected element. scefoundmask , cpefoundmask , and lfefoundmask indicate which elements have been found in an aac stream since the variables have last been cleared. the values can be used to present an element selection menu with only the available elements. dyncompress and dynboost change the behavior of the dynamic range control (drc) that is present in some aac streams. these are also initialized when aac decoding starts. sci hdat0 contains the average bitrate in bytes per second, is updated once per second and it can be used to calculate an estimate of the remaining playtime. 9.8.4 midi parameter address usage midicon?g 0x1943 miscellaneous con?guration bits [3:0] reverb: 0 = auto (on if clock > = 3 : 0 ) 1 = off, 2 - 15 = room size bits [6:4] play speed: 0 = 1 , 1 = 2 , 2 = 4 , 3 = 8 .. 7 = 128 bits [15:7] reserved bytesleft 0x196a/6b the number of bytes left in this track midiconfig controls the reverb effect and play speed. sci hdat0 contains the average bitrate in bytes per second, is updated once per second and it can be used together with bytesleft to calculate an estimate of the remaining playtime. version 0.6, 2005-01-05 48 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.9 fast forward / rewind 9.9.1 mp3 mpeg1.0 and mpeg2.0 layer 3 de?nes a stream format suitable for random-access. when you want to skip forward or backwards in the ?le, ?rst send 2048 zeros, then continue sending the ?le from the new location. by sending zeros you make certain a partial frame does not cause loud artefacts in the sound. the normal ?le type checking then ?nds a new mp3 header and continues decoding. 9.9.2 aac - adts mpeg2.0 advanced audio coded (aac) de?nes a stream format suitable for random-access (adts). when you want to skip forward or backwards in the ?le, ?rst send 2048 zeros, then continue sending the ?le from the new location. by sending zeros you make certain a partial frame does not cause loud artefacts in the sound. the normal ?le type checking then ?nds a new adts header and continues decoding. 9.9.3 aac - adif, mp4 mpeg4.0 advanced audio codec (aac) speci?es a multimedia ?le format (.mp4 / .m4a) but does not specify a stream format and mpeg2.0 aac speci?es a ?le format (adif) in addition to the streamable adts format. adif and .mp4 / .m4a are not suitable for random-access and it is recommended that they are converted to adts format for playback. however, it is also possible to implement fast forward and rewind for adif and .mp4 / .m4a ?les. the easiest way is to use the resync ?eld (see section 9.8.1): 2 write 8192 to resync C write 0x1969 to sci wramaddr, write 0x2000 to sci wram 2 send 2048 zeroes 2 make a seek x in the ?le ( x > 0 for forward seek) 2 indicate the low part of the seek amount by writing to seek1 C write 0x1967 to sci wramaddr, write ( x ? 2048)&1023 to sci wram 2 indicate the high part of the seek amount by writing to seek2 C write 0x1968 to sci wramaddr, write ( x ? 2048) = 1024 to sci wram 2 continue sending the ?le from the new location perfect fast forward and rewind can be implemented by using the jumppoints table and making seeks only on packet or data block boundaries. version 0.6, 2005-01-05 49 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.9.4 wma windows media audio (wma) is enclosed as data packets into advanced systems format (asf) ?les. this ?le format is not suitable for random-access. however, it is also possible to implement fast forward and rewind for wma ?les. the easiest way is to use the resync ?eld (see section 9.9.3), perfect fast forward and rewind can be implemented by using the jumppoints table and making seeks only on packet or data block boundaries. 9.9.5 midi midi is not at all suitable for random-access. you can implement fast forward using the playspeed bits of the midiconfig ?eld to select 1-128 play speed. sci decode time also speeds up. if necessary, rewind can be implemented by restarting the decoding of a midi ?le and fast forwarding to the appropriate place. sci decode time can be used to decide when the right place has been reached. this is best suited for soundless rewind. version 0.6, 2005-01-05 50 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.10 sdi tests there are several test modes in VS1033, which allow the user to perform memory tests, sci bus tests, and several different sine wave tests. all tests are started in a similar way: VS1033 is hardware reset, sm tests is set, and then a test command is sent to the sdi bus. each test is started by sending a 4-byte special command sequence, followed by 4 zeros. the sequences are described below. 9.10.1 sine test sine test is initialized with the 8-byte sequence 0x53 0xef 0x6e n 0 0 0 0, where n de?nes the sine test to use. n is de?ned as follows: n bits name bits description f s idx 7:5 sample rate index s 4:0 sine skip speed f s idx f s 0 44100 hz 1 48000 hz 2 32000 hz 3 22050 hz 4 24000 hz 5 16000 hz 6 11025 hz 7 12000 hz the frequency of the sine to be output can now be calculated from f = f s s 128 . example: sine test is activated with value 126, which is 0b01111110. breaking n to its components, f s idx = 0 b 011 = 3 and thus f s = 22050 hz . s = 0 b 11110 = 30 , and thus the ?nal sine frequency f = 22050 hz 30 128 ? 5168 hz . to exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0. note: sine test signals go through the digital volume control, so it is possible to test channels separately. 9.10.2 pin test pin test is activated with the 8-byte sequence 0x50 0xed 0x6e 0x54 0 0 0 0. this test is meant for chip production testing only. version 0.6, 2005-01-05 51 vlsi solution y
VS1033a preliminary VS1033 a 9. operation 9.10.3 memory test memory test mode is initialized with the 8-byte sequence 0x4d 0xea 0x6d 0x54 0 0 0 0. after this sequence, wait for 500000 clock cycles. the result can be read from the sci register sci hdat0, and one bits are interpreted as follows: bit(s) mask meaning 15 0x8000 test ?nished 14:7 unused 6 0x0040 mux test succeeded 5 0x0020 good i ram 4 0x0010 good y ram 3 0x0008 good x ram 2 0x0004 good i rom 1 0x0002 good y rom 0 0x0001 good x rom 0x807f all ok memory tests overwrite the current contents of the ram memories. 9.10.4 sci test sci test is initialized with the 8-byte sequence 0x53 0x70 0xee n 0 0 0 0, where n ? 48 is the register number to test. the content of the given register is read and copied to sci hdat0. if the register to be tested is hdat0, the result is copied to sci hdat1. example: if n is 48, contents of sci register 0 (sci mode) is copied to sci hdat0. version 0.6, 2005-01-05 52 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10 VS1033 registers 10.1 who needs to read this chapter user software is required when a user wishes to add some own functionality like dsp effects to VS1033. however, most users of VS1033 dont need to worry about writing their own code, or about this chapter, including those who only download software plug-ins from vlsi solutions web site. 10.2 the processor core vs dsp is a 16/32-bit dsp processor core that also had extensive all-purpose processor features. vlsi solutions free vskit software package contains all the tools and documentation needed to write, sim- ulate and debug assembly language or extended ansi c programs for the vs dsp processor core. vlsi solution also offers a full integrated development environment vside for full debug capabilities. 10.3 VS1033 memory map VS1033s memory map is shown in figure 14. 10.4 sci registers sci registers described in chapter 8.6 can be found here between 0xc000..0xc00f. in addition to these registers, there is one in address 0xc010, called sci change. sci registers, pre?x sci reg type reset abbrev[bits] description 0xc010 r 0 change[5:0] last sci access address sci change bits name bits description sci ch write 4 1 if last access was a write cycle sci ch addr 3:0 sci address of last access 10.5 serial data registers sdi registers, pre?x ser reg type reset abbrev[bits] description 0xc011 r 0 data last received 2 bytes, big-endian 0xc012 w 0 dreq[0] dreq pin control version 0.6, 2005-01-05 53 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers figure 14: users memory map. 10.6 dac registers dac registers, pre?x dac reg type reset abbrev[bits] description 0xc013 rw 0 fctll dac frequency control, 16 lsbs 0xc014 rw 0 fctlh dac frequency control 4msbs, pll control 0xc015 rw 0 left dac left channel pcm value 0xc016 rw 0 right dac right channel pcm value every fourth clock cycle, an internal 26-bit counter is added to by (dac fctlh & 15) 65536 + dac fctll. whenever this counter over?ows, values from dac left and dac right are read and a dac interrupt is generated. version 0.6, 2005-01-05 54 0000 0000 instruction (32?bit) y (16?bit) x (16?bit) system vectors userinstruction ram x data ram y data ram 0030 0030 y data rom x data rom 4000 4000 instruction rom c000c100 c100 c000 0500 0500 8000 8000 stack stack 1940 1880 1800 18001880 1940 2800 2000 2800 2000 ffff ffff i/o user user vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.7 gpio registers gpio registers, pre?x gpio reg type reset abbrev[bits] description 0xc017 rw 0 ddr[7:0] direction 0xc018 r 0 idata[7:0] values read from the pins 0xc019 rw 0 odata[7:0] values set to the pins gpio dir is used to set the direction of the gpio pins. 1 means output. gpio odata remembers its values even if a gpio dir bit is set to input. gpio registers dont generate interrupts. note that in VS1033 the vsdsp registers can be read and written through the sci wramaddr and sci wram registers. you can thus use the gpio pins quite conveniently. version 0.6, 2005-01-05 55 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.8 interrupt registers interrupt registers, pre?x int reg type reset abbrev[bits] description 0xc01a rw 0 enable[7:0] interrupt enable 0xc01b w 0 glob dis[-] write to add to interrupt counter 0xc01c w 0 glob ena[-] write to subtract from interrupt counter 0xc01d rw 0 counter[4:0] interrupt counter int enable controls the interrupts. the control bits are as follows: int enable bits name bits description int en tim1 7 enable timer 1 interrupt int en tim0 6 enable timer 0 interrupt int en rx 5 enable uart rx interrupt int en tx 4 enable uart tx interrupt int en modu 3 enable ad modulator interrupt int en sdi 2 enable data interrupt int en sci 1 enable sci interrupt int en dac 0 enable dac interrupt note: it may take upto 6 clock cycles before changing int enable has any effect. writing any value to int glob dis adds one to the interrupt counter int counter and effectively disables all interrupts. it may take upto 6 clock cycles before writing to this register has any effect. writing any value to int glob ena subtracts one from the interrupt counter (unless int counter already was 0). if the interrupt counter becomes zero, interrupts selected with int enable are re- stored. an interrupt routine should always write to this register as the last thing it does, because in- terrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the responsibility of the user. it may take upto 6 clock cycles before writing this register has any effect. by reading int counter the user may check if the interrupt counter is correct or not. if the register is not 0, interrupts are disabled. version 0.6, 2005-01-05 56 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.9 a/d modulator registers interrupt registers, pre?x ad reg type reset abbrev[bits] description 0xc01e rw 0 div a/d modulator divider 0xc01f rw 0 data a/d modulator data ad div bits name bits description adm powerdown 15 1 in powerdown adm divider 14:0 divider adm divider controls the ad converters sampling frequency. to gather one sample, 128 n clock cycles are used ( n is value of ad div). the lowest usable value is 4, which gives a 48 khz sample rate when clki is 24.576 mhz. when adm powerdown is 1, the a/d converter is turned off. ad data contains the latest decoded a/d value. version 0.6, 2005-01-05 57 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.10 watchdog v1.0 2002-08-26 the watchdog consist of a watchdog counter and some logic. after reset, the watchdog is inactive. the counter reload value can be set by writing to wdog config. the watchdog is activated by writ- ing 0x4ea9 to register wdog reset. every time this is done, the watchdog counter is reset. every 65536th clock cycle the counter is decremented by one. if the counter under?ows, it will activate vs- dsps internal reset sequence. thus, after the ?rst 0x4ea9 write to wdog reset, subsequent writes to the same register with the same value must be made no less than every 65536 wdog config clock cycles. once started, the watchdog cannot be turned off. also, a write to wdog config doesnt change the counter reload value. after watchdog has been activated, any read/write operation from/to wdog config or wdog dummy will invalidate the next write operation to wdog reset. this will prevent runaway loops from re- setting the counter, even if they do happen to write the correct number. writing a wrong value to wdog reset will also invalidate the next write to wdog reset. reads from watchdog registers return unde?ned values. 10.10.1 registers watchdog, pre?x wdog reg type reset abbrev description 0xc020 w 0 config con?guration 0xc021 w 0 reset clock con?guration 0xc022 w 0 dummy[-] dummy register version 0.6, 2005-01-05 58 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.11 uart v1.1 2004-10-09 rs232 uart implements a serial interface using rs232 standard. figure 15: rs232 serial interface protocol when the line is idling, it stays in logic high state. when a byte is transmitted, the transmission begins with a start bit (logic zero) and continues with data bits (lsb ?rst) and ends up with a stop bit (logic high). 10 bits are sent for each 8-bit byte frame. 10.11.1 registers uart registers, pre?x uartx reg type reset abbrev description 0xc028 r 0 status[4:0] status 0xc029 r/w 0 data[7:0] data 0xc02a r/w 0 datah[15:8] data high 0xc02b r/w 0 div divider 10.11.2 status uartx status a read from the status register returns the transmitter and receiver states. uartx status bits name bits description uart st frameerr 4 framing error (stop bit was 0) uart st rxorun 3 receiver overrun uart st rxfull 2 receiver data register full uart st txfull 1 transmitter data register full uart st txrunning 0 transmitter running uart st frameerr is set if the stop bit of the received byte was 0. uart st rxorun is set if a received byte overwrites unread data when it is transferred from the receiver shift register to the data register, otherwise it is cleared. uart st rxfull is set if there is unread data in the data register. uart st txfull is set if a write to the data register is not allowed (data register full). uart st txrunning is set if the transmitter shift register is in operation. version 0.6, 2005-01-05 59 vlsi solution y startbit d0 d1 d2 d3 d4 d5 d6 d7 stopbit
VS1033a preliminary VS1033 a 10. VS1033 registers 10.11.3 data uartx data a read from uartx data returns the received byte in bits 7:0, bits 15:8 are returned as 0. if there is no more data to be read, the receiver data register full indicator will be cleared. a receive interrupt will be generated when a byte is moved from the receiver shift register to the receiver data register. a write to uartx data sets a byte for transmission. the data is taken from bits 7:0, other bits in the written value are ignored. if the transmitter is idle, the byte is immediately moved to the transmitter shift register, a transmit interrupt request is generated, and transmission is started. if the transmitter is busy, the uart st txfull will be set and the byte remains in the transmitter data register until the previous byte has been sent and transmission can proceed. 10.11.4 data high uartx datah the same as uartx data, except that bits 15:8 are used. 10.11.5 divider uartx div uartx div bits name bits description uart div d1 15:8 divider 1 (0..255) uart div d2 7:0 divider 2 (6..255) the divider is set to 0x0000 in reset. the rom boot code must initialize it correctly depending on the master clock frequency to get the correct bit speed. the second divider ( d 2 ) must be from 6 to 255. the communication speed f = f m ( d 1 +1) ( d 2 ) , where f m is the master clock frequency, and f is the tx/rx speed in bps. divider values for common communication speeds at 26 mhz master clock: example uart speeds, f m = 26 m hz comm. speed [bps] uart div d1 uart div d2 4800 85 63 9600 42 63 14400 42 42 19200 51 26 28800 42 21 38400 25 26 57600 1 226 115200 0 226 version 0.6, 2005-01-05 60 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.11.6 interrupts and operation transmitter operates as follows: after an 8-bit word is written to the transmit data register it will be transmitted instantly if the transmitter is not busy transmitting the previous byte. when the transmission begins a tx intr interrupt will be sent. status bit [1] informs the transmitter data register empty (or full state) and bit [0] informs the transmitter (shift register) empty state. a new word must not be written to transmitter data register if it is not empty (bit [1] = 0). the transmitter data register will be empty as soon as it is shifted to transmitter and the transmission is begun. it is safe to write a new word to transmitter data register every time a transmit interrupt is generated. receiver operates as follows: it samples the rx signal line and if it detects a high to low transition, a start bit is found. after this it samples each 8 bit at the middle of the bit time (using a constant timer), and ?lls the receiver (shift register) lsb ?rst. finally the data in the receiver is moved to the reveive data register, the stop bit state is checked (logic high = ok, logic low = framing error) for status bit[4], the rx intr interrupt is sent, status bit[2] (receive data register full) is set, and status bit[2] old state is copied to bit[3] (receive data overrun). after that the receiver returns to idle state to wait for a new start bit. status bit[2] is zeroed when the receiver data register is read. rs232 communication speed is set using two clock dividers. the base clock is the processor master clock. bits 15-8 in these registers are for ?rst divider and bits 7-0 for second divider. rx sample frequency is the clock frequency that is input for the second divider. version 0.6, 2005-01-05 61 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.12 timers v1.0 2002-04-23 there are two 32-bit timers that can be initialized and enabled independently of each other. if enabled, a timer initializes to its start value, written by a processor, and starts decrementing every clock cycle. when the value goes past zero, an interrupt is sent, and the timer initializes to the value in its start value register, and continues downcounting. a timer stays in that loop as long as it is enabled. a timer has a 32-bit timer register for down counting and a 32-bit timer1 lh register for holding the timer start value written by the processor. timers have also a 2-bit timer ena register. each timer is enabled (1) or disabled (0) by a corresponding bit of the enable register. 10.12.1 registers timer registers, pre?x timer reg type reset abbrev description 0xc030 r/w 0 config[7:0] timer con?guration 0xc031 r/w 0 enable[1:0] timer enable 0xc034 r/w 0 t0l timer0 startvalue - lsbs 0xc035 r/w 0 t0h timer0 startvalue - msbs 0xc036 r/w 0 t0cntl timer0 counter - lsbs 0xc037 r/w 0 t0cnth timer0 counter - msbs 0xc038 r/w 0 t1l timer1 startvalue - lsbs 0xc039 r/w 0 t1h timer1 startvalue - msbs 0xc03a r/w 0 t1cntl timer1 counter - lsbs 0xc03b r/w 0 t1cnth timer1 counter - msbs 10.12.2 con?guration timer config timer config bits name bits description timer cf clkdiv 7:0 master clock divider timer cf clkdiv is the master clock divider for all timer clocks. the generated internal clock frequency f i = f m c +1 , where f m is the master clock frequency and c is timer cf clkdiv. example: with a 12 mhz master clock, timer cf div=3 divides the master clock by 4, and the output/sampling clock would thus be f i = 12 m hz 3+1 = 3 m hz . version 0.6, 2005-01-05 62 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.12.3 con?guration timer enable timer enable bits name bits description timer en t1 1 enable timer 1 timer en t0 0 enable timer 0 10.12.4 timer x startvalue timer tx[l/h] the 32-bit start value timer tx[l/h] sets the initial counter value when the timer is reset. the timer interrupt frequency f t = f i c +1 where f i is the master clock obtained with the clock divider (see chap- ter 10.12.2 and c is timer tx[l/h]. example: with a 12 mhz master clock and with timer cf clkdiv=3, the master clock f i = 3 m hz . if timer th=0, timer tl=99, then the timer interrupt frequency f t = 3 m hz 99+1 = 30 khz . 10.12.5 timer x counter timer txcnt[l/h] timer txcnt[l/h] contains the current counter values. by reading this register pair, the user may get knowledge of how long it will take before the next timer interrupt. also, by writing to this register, a one-shot different length timer interrupt delay may be realized. 10.12.6 interrupts each timer has its own interrupt, which is asserted when the timer counter under?ows. version 0.6, 2005-01-05 63 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.13 i2s dac interface the i2s interface makes it possible to attach an external dac to the system. 10.13.1 registers i2s registers, pre?x i2s reg type reset abbrev description 0xc040 r/w 0 config[3:0] i2s con?guration 10.13.2 con?guration i2s config i2s config bits name bits description i2s cf mclk ena 3 enables the mclk output (12.288 mhz) i2s cf ena 2 enables i2s, otherwise pins are gpio i2s cf srate 1:0 i2s rate, 10 = 192, 01 = 96, 00 = 48 khz i2s cf ena enables the i2s interface. after reset the interface is disabled and the pins are used for gpio. i2s cf mclk ena enables the mclk output. the frequency is either directly the input clock (nom- inal 12.288 mhz), or half the input clock when mode register bit sm clk range is set to 1 (24- 26 mhz input clock). i2s cf srate controls the output samplerate. when set to 48 khz, sclk is mclk divided by 8, when 96 khz sclk is mclk divided by 4, and when 192 khz sclk is mclk divided by 2. figure 16: i2s interface, 192 khz. to enable i2s ?rst write 0xc017 to sci wramaddr and 0x33 to sci wram, then write 0xc040 to sci wramaddr and 0x0c to sci wram. version 0.6, 2005-01-05 64 vlsi solution y mclksdata sclklrout msb lsb msb left channel word right channel word
VS1033a preliminary VS1033 a 10. VS1033 registers 10.14 system vector tags the system vector tags are tags that may be replaced by the user to take control over several decoder functions. 10.14.1 audioint, 0x20 normally contains the following vs dsp assembly code: jmpi dac_int_address,(i6)+1 the user may, at will, replace the ?rst instruction with a jmpi command to gain control over the audio interrupt. 10.14.2 sciint, 0x21 normally contains the following vs dsp assembly code: jmpi sci_int_address,(i6)+1 the user may, at will, replace the instruction with a jmpi command to gain control over the sci interrupt. 10.14.3 dataint, 0x22 normally contains the following vs dsp assembly code: jmpi sdi_int_address,(i6)+1 the user may, at will, replace the instruction with a jmpi command to gain control over the sdi interrupt. 10.14.4 moduint, 0x23 normally contains the following vs dsp assembly code: jmpi modu_int_address,(i6)+1 the user may, at will, replace the instruction with a jmpi command to gain control over the ad modu- lator interrupt. version 0.6, 2005-01-05 65 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.14.5 txint, 0x24 normally contains the following vs dsp assembly code: jmpi empty_int_address,(i6)+1 the user may, at will, replace the instruction with a jmpi command to gain control over the uart tx interrupt. 10.14.6 rxint, 0x25 normally contains the following vs dsp assembly code: jmpi rx_int_address,(i6)+1 the user may, at will, replace the ?rst instruction with a jmpi command to gain control over the uart rx interrupt. 10.14.7 timer0int, 0x26 normally contains the following vs dsp assembly code: jmpi empty_int_address,(i6)+1 the user may, at will, replace the ?rst instruction with a jmpi command to gain control over the timer 0 interrupt. 10.14.8 timer1int, 0x27 normally contains the following vs dsp assembly code: jmpi empty_int_address,(i6)+1 the user may, at will, replace the ?rst instruction with a jmpi command to gain control over the timer 1 interrupt. version 0.6, 2005-01-05 66 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers 10.14.9 usercodec, 0x0 normally contains the following vs dsp assembly code: jr nop if the user wants to take control away from the standard decoder, the ?rst instruction should be replaced with an appropriate j command to users own code. unless the user is feeding mp3 or wma data at the same time, the system activates the user program in less than 1 ms. after this, the user should steal interrupt vectors from the system, and insert user programs. 10.15 system vector functions the system vector functions are pointers to some functions that the user may call to help implementing his own applications. 10.15.1 writeiram(), 0x2 vs dsp c prototype: void writeiram(register i0 u int16 *addr, register a1 u int16 msw, register a0 u int16 lsw); this is the preferred way to write to the user instruction ram. 10.15.2 readiram(), 0x4 vs dsp c prototype: u int32 readiram(register i0 u int16 *addr); this is the preferred way to read from the user instruction ram. a1 contains the msbs and a0 the lsbs of the result. 10.15.3 databytes(), 0x6 vs dsp c prototype: version 0.6, 2005-01-05 67 vlsi solution y
VS1033a preliminary VS1033 a 10. VS1033 registers u int16 databytes(void); if the user has taken over the normal operation of the system by switching the pointer in usercodec to point to his own code, he may read data from the data interface through this and the following two functions. this function returns the number of data bytes that can be read. 10.15.4 getdatabyte(), 0x8 vs dsp c prototype: u int16 getdatabyte(void); reads and returns one data byte from the data interface. this function will wait until there is enough data in the input buffer. 10.15.5 getdatawords(), 0xa vs dsp c prototype: void getdatawords(register i0 y u int16 *d, register a0 u int16 n); read n data byte pairs and copy them in big-endian format (?rst byte to msbs) to d . this function will wait until there is enough data in the input buffer. 10.15.6 reboot(), 0xc vs dsp c prototype: void reboot(void); causes a software reboot, i.e. jump to the standard ?rmware without reinitializing the iram vectors. this is not the same as the software reset function, which causes complete initialization. version 0.6, 2005-01-05 68 vlsi solution y
VS1033a preliminary VS1033 a 11. document version changes 11 document version changes this chapter describes the most important changes to this document. 11.1 version 0.6 for VS1033a, 2005-01-05 2 adpcm recording section added (section 9.4) 11.2 version 0.5, 2005-10-21 2 more detailed info about fast forward / rewind. version 0.6, 2005-01-05 69 vlsi solution y
VS1033a preliminary VS1033 a 12. contact information 12 contact information vlsi solution oy hermiankatu 6-8 c fin-33720 tampere finland fax: +358-3-316 5220 phone: +358-3-316 5230 email: sales@vlsi.? url: http://www.vlsi.?/ version 0.6, 2005-01-05 70 vlsi solution y

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